Axis Jobs
Sr Principal Design Engineer, Digital IP
L&T Semiconductor Technologies - Bengaluru, Karnataka, India
Integration, RTL signoff tools and CDC/RDC/Lint/Synthesis. Familiarity with Computer architecture: knowledge of microprocessors, bus protocols preferred (AXI/ACE/APB/ATB). Knowledge on CPU architecture
from: linkedin.com - 2 days ago
Sr. Principal Verification Engineer
L&T Semiconductor Technologies - Bengaluru, Karnataka, India
IP, Design Enablement, Emulation, and Validation to achieve project milestones Strong Knowledge of protocols such as Ethernet/802.3, PCIe, MIPI, PHY IPs, etc , AMBA, CHI, ACE, AXI bus protocols , VHDL
from: linkedin.com - 2 days ago
Design Verification Engineer - System Verilog/UVM
Bangalore, Karnataka, IN
and Experience: - Team leadership and mentoring experience - Multiprocessing microarchitecture experience including knowledge of cache coherence and bus protocols (e.g. AMBA 5 CHI, AMBA 4 ACE or AXI) - Experience
from: adzuna.in - 3 days ago
RTL Design Lead
Wipro - Greater Bengaluru Area
understanding of AMBA bus protocols (AXI, AHB, ATB, APB). Good understanding of timing concepts. Knowledge of one or more of the interface protocols, PCIe, DDR, Ethernet, I2C, UART, SPI. Expertise in setting up
from: linkedin.com - 2 days ago
Design Verification Engineer
Capgemini - Bengaluru, Karnataka, India
, Functional coverage, GLS, LEC, Emulation, AMS, ARM, Protocols AHB/AXI/APB, Ethernet, USB, PCIe, I2C, SPI, CAN, Mipi CSI/DSI, LPDDR.
from: linkedin.com - 2 days ago
VLSI Design Engineer - SoC/RTL Design
Dotflick Solutions - India, IN (+1 location)
in working with AMBA Bus- AXI, AHB, APB - In-depth understanding of Verilog/VHDL and ARM So C architecture - Hands-on experience and expert-level knowledge in ASIC Synthesis - Participate in So C
from: adzuna.in (+1 source) - 3 days ago
CPU Verification ( RISC-V /ARM / MIPS )
Mulya Technologies - Greater Bengaluru Area (+1 location)
/GPU/DSP area Exposure to various ASIC design and verification tools with good digital design concepts Experience with Interconnect protocols like AXI/ACE/ CHI/OCP Scripting experience in Python/Perl/TCL
from: linkedin.com (+1 source) - 2 days ago
Processor Architecture and Logic design : Fabric Lead
Mulya Technologies - Greater Bengaluru Area
Required Technical and Professional Expertise 8+ years of relevant experience At least 1 generation of processor interconnect design delivery leadership (eg UPI, axi, amba, NoC). Expertise of SMP coherency
from: linkedin.com - 2 days ago
Design Verification Engineer - NOC
VIPSA TALENT SOLUTIONS PRIVATE LIMITED - Bangalore, Karnataka, IN
in Clocking/Boot/Reset Flows. 4. Experience in System Verilog and UVM is a must. 5. Experience in ARM Protocols - AXI, AHB and CHI. 6. Familiarity with scripting languages like Perl, Python. Required Education
from: adzuna.in (+1 source) - 3 days ago
PV Design Engineer (Electrical)
Solarpro Holding - Ahmedabad, Gujarat, India
(Balance of Plant) for solar PV projects with various technology (such as string inverter, central inverter, Single Axis tracker system, bifacial PV modules, Fixed type mounting supporting structure etc
from: linkedin.com - 2 days ago
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