Chip Level Jobs

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Analog Layout | 4 to 10 Years | Bangalore  

Capgemini Engineering - Bengaluru, Karnataka, India

and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, EM, quality check and documentation. Responsible for on-time delivery of block-level/top-level layouts

from: linkedin.com - 6 days ago

(STA) Engineer PostLayout / Pre Layout STA (Timing Closure) TCL Scripting 6+ Years Bangalore  

Tech Mahindra - Bengaluru, Karnataka, India

STA (Constraints generation and validation) PostLayout STA (Timing Closure) very good in TCL Scripting. Job description: Full chip and block level timing closure ownership throughout the entire project

from: linkedin.com - 8 days ago

Lead Engineer SoC Verification  

Bengaluru, Karnataka, India

well as part of a team both locally, and with remote or multi-site teams Key Skills 7+ years of experience on SOC/Chip level/Cluster/Sub-System Verification Experience in Microcontroller

from: jobleads.co.in - Yesterday

SOC Verification Lead  

Renesas Electronics - Hyderabad, Telangana, India

, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity and inclusion Qualifications Required 14+ years of pre-silicon SOC/chip level, Subsystem, or IP verification

from: linkedin.com - 8 days ago

Emulation Lead  

Wipro - Bengaluru, Karnataka, India

emulation users Must have worked in end-to-end Emulation of atleast 1-2 SoC programs in Sub-system and chip level. Locations: India, Hyd, Delhi (NCR), Chennai, Bangalore, Pune, Kochi, Mumbai, Etc).

from: linkedin.com - 6 days ago

Physical Design Engineer I 4 to 6 years | Bangalore  

Capgemini - Hyderabad, KA, IN (+2 locations)

Job Description: Chip level floorplanning, partitioning, timing budget generations, power planning, top PnR, CTS, block integration and ECO generation. Hands on experience in ICC and primetime. Block

from: Capgemini (+1 source) - 24 days ago

SoC Verification -Staff Engineer  

Silicon Labs - Hyderabad, Telangana, India

on architecture of chip-level testbenches and verification of SoCs and chipsets with ARM Cortex and proprietary processor technology and AMBA AHB/AXI/APB along with peripheral interfaces like SDIO, UART, I2S, I2C

from: linkedin.com - 14 days ago

CPU Verification Engineer  

Wafer Space - An ACL Digital Company - Bengaluru, Karnataka, India

. • Familiarity with defining block level and chip level testing infrastructure. • Skilled in using industry standard HDL languages ( System Verilog , Verilog, VHDL) and simulation tools is a must. • Experience

from: linkedin.com - 21 days ago

RTL Synthesis & Data Analyst - System Verilog  

Bangalore, India

and STA tools. Should have prior working experience at both IP and full-chip levels and should have supported in tape-out activities- Should have experience in pre-layout and post-layout timing analysis 27

from: hirist.com - 6 days ago

Verification Lead  

Cyient - Bangalore Urban, Karnataka, India

Design Verification Lead Job Location: Hyderabad / Bangalore. – 100% Work from Office - No hybrid. Experience: Min 10+ years to 18 years. Skills: Block level, full chip verification experience using

from: linkedin.com - 21 days ago


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