Static Jobs in Pune

UST - Pune, Maharashtra, India

Creation and Execution. Polyspace configuration with different compilers. Run time analysis experience. Static analysis experience. QAC configuration with different compilers. Experience in Automotive domain.

from: linkedin.com - 9 days ago

Invokhr - Pune, Maharashtra, IN

, Webserver. - Experience in RTOS platform, address Cyber-security requirements, fix the issues reported by static code anaysis tools like Coverity or parasoft. - Hands-on experience in developing application

from: adzuna.in - 3 days ago

Geminus Tech - Pune, Maharashtra, India

tools such as Coverity for static analysis to identify and rectify potential code vulnerabilities. Misra C++ Compliance: Ensure compliance with Misra C++ standards, particularly those relevant

from: linkedin.com - 17 days ago

Wipro - Pune, Maharashtra, India

and devices. Possesses SME/ "deep" experience in enterprise PIM, including but not limited to user onboarding, application onboarding. Experience in designing request workflows for on demand and static Azure

from: linkedin.com - 18 days ago

Sampoorna Consultants Pvt. Ltd - Pune, Maharashtra, IN

balancing - Well versed with Routing protocols - static routes, IS-IS (v 4/v 6), RIPv 2/ng, OSPF v 2/v 3, BGP 4 - Experience on working with hypervisor; for example, VMware, ESXi, Microsoft Hyper-V, and KVM

from: adzuna.in - 11 days ago

VTP Realty - Pune, Maharashtra, India

in design of steel Structures. Hands on experience in various design software ETABS, SAFE, STAAD PRO Etc. Experience in static and dynamic analysis of ETABS model & design of various structural Elements

from: linkedin.com (+1 source) - 19 days ago

Cadence Design Systems - Pune, Maharashtra, India

, APB Experience on cadence tools Exposure to Lint/CDC, Synthesis, Static Timing Analysis review Exposure to all major IC implementation, design, and verification tools. Willing to travel to customer

from: linkedin.com - 27 days ago

Kiash Solutions LLp - Bangalore/Hyderabad/Pune, India

and signoff at the block level, particularly at 16/7nm technology nodes. Key responsibilities include floor planning, clock tree synthesis (CTS), static timing analysis (STA), physical verification, and a basic 40

from: hirist.com - 17 days ago

Cadence Design Systems - Pune, Maharashtra, India

, APB Experience on cadence tools Exposure to Lint/CDC, Synthesis, Static Timing Analysis review Exposure to all major IC implementation, design, and verification tools. Willing to travel to customer

from: linkedin.com (+1 source) - 29 days ago

Cadence Design Systems - Pune, Maharashtra, India

-micron technology issues. · Solid knowledge of LP Design, DFT, static timing analysis, EM/IR-Drop/crosstalk analysis, formal verification, physical verification, and DFM. · Successful track records

from: linkedin.com - More than 30 days ago