Verilog Jobs in Pune
Mixed Signal Design Engineer
VASBEAM Private Limited - Pune, Maharashtra, India
custom IC EDA tools. Proficiency in system and behavioral modeling using MATLAB, System Verilog, Verilog-A/AMS. Desired familiarity with HDL languages Verilog and/or VHDL. Proficient in scripting languages
from: linkedin.com - 5 days ago
Mixed Signal ASIC Design
VASBEAM Pvt Ltd - Pune, Maharashtra, India
and behavioural modeling using MATLAB, System Verilog, Verilog-A/AMS. Experience with HDL languages Verilog and/or VHDL is desired. Scripting skills: Python, Perl and C is a plus. ยท Experience with design
from: linkedin.com (+1 source) - 23 days ago
Mixed Signal ASIC Design Lead - System Verilog
ACZ Global Private Limited - Pune, India
of more than 5 ASIC designs- In depth knowledge of Cadence custom IC EDA tools- Proficiency in system and behavioural modeling using MATLAB, System Verilog, Verilog-A/AMS.- Experience with HDL languages 40
from: hirist.com (+1 source) - 21 days ago
GVR TECHNOLABS PRIVATE LIMITED - Pune, IN
/ Verilog/ VHDL code review and reporting Third party library testing and report generation Verification of software tool qualification and documentation Impact analysis and change request-based testing 30000 - 600000 per month
from: expertia.ai - More than 30 days ago
Senior FPGA Design Engineer
Tudip Technologies - Pune, Maharashtra, India
, including VLAN tagging, frame forwarding, MAC address learning, and multicast filtering. Implement RTL code for Ethernet switch features using Verilog or VHDL, ensuring high performance and low latency
from: jobleads.co.in (+1 source) - More than 30 days ago
GVR TECHNOLABS PRIVATE LIMITED - Pune, IN
and review and reporting FPGA/ Verilog/ VHDL code review and reporting Third party library testing and report generation Verification of software tool qualification and documentation Impact analysis and change 20000 - 23000 per month
from: expertia.ai - More than 30 days ago
Principal Verification Engineer
Marvell India - Other Maharashtra,Pune
or related fields with 5-10 years of experience. Hands-on experience on using Verilog, System Verilog and UVM (Universal Verification Methodology) Good scripting skills in languages such as Perl, Tcl
from: Shine.com - 16 days ago
Agiliad Technologies - Pune
solutions with external GPU/HPC architectures. Strong programming skills in hardware description languages (e.g., Verilog, VHDL) and experience with FPGA development tools. Familiarity with GPU programming Not disclosed INR
from: naukri.com - 16 days ago
ASIC Digital Design, Principal Engineer
Sypnosys - Pune, India
will be involved at specify, verification and implement phases of state-of-the-art products. Key responsibilities: Identify verification environment requirements from its various sources (Specifications, Design Not Mentioned
from: Monsterindia.com - 27 days ago
ASIC Digital Design, Staff Engineer
Sypnosys - Pune, India
in the following areas: - Must have experience in developing HVL (System Verilog) based test environments, developing, and implementing test plans, implementing, and extracting verification metrics Not Mentioned
from: Monsterindia.com - More than 30 days ago
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