1,824 Nms Jobs - page 2
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Physical Design Engineer L&T Technology Services - Bengaluru, Karnataka, India ), signoff checks like FEV, VCLP, EMIR and PV. Knowledge of industry standard EDA tools (Synopsys, Cadence, Mentor) Worked on DSM technologies, tsmc 5nm and below experience preferred. Knowledge of scripting 2 days ago
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DFT Design Engineer eInfochips (An Arrow Company) - , , India on latest technology (28nm,16nm,7 nm) EDUCATION BACKGROUND · B.E./ B.S./ B.Tech/ M.S./ M.Tech in VLSI/Electronics/Electrical/Computer/Instrumentation Engineering. ABOUT eInfochips (An Arrow Company Yesterday
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Senior Staff, CAD Engineer (RTL-to-GDS implementation flow) Synopsys - , , India design. Synopsys Inc. is a leading provider of electronic design automation (EDA) software and services, working on cutting edge technologies and most advanced nodes (5nm, 3nm, 2nm and below). Main Yesterday
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STA Engineer L&T Technology Services - Bengaluru, Karnataka, India from Synopsys or Cadence. Worked on DSM technologies, tsmc 5nm and below experience preferred. Minimum 5+ years of relevant experience. Good scripting and communication skills. 2 days ago
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Digital Circuit design Cognitive Design Technology Pvt Ltd - Bengaluru, Karnataka, India of a team that is building standard cells in advanced nodes (e.g., 12nm and beyond). · Work with product development teams (library characterization, Engineering, Architecture and Product Planning team 4 days ago
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Physical Design Innovus Expert Engineer Mirafra Technologies - , , India , and with automation with lower nodes like 7nm. Strong scripting skills in Innovus- TCL, and Python/Perl(optional) Top down floorplan and Power Grid understanding for development methodology is a must Experience Yesterday
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AMS Layout - Sr. Engineer to Technical Manager Cyient - Hyderabad, Telangana, India Excellent work experience in Analog / Mixed Signal Layout design in advanced FinFET processes like 16nm, 12nm, 10nm, 7nm, 5nm, 3nm Hands on experience in any or multiple critical blocks 7 days ago
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Analog Layout design MosChip - Hyderabad, Telangana, India nodes TSMC 3nm, 5nm & Intel 5nm. • Exposure on knowledge of basic circuits, matching constraints & shielding techniques required for highspeed layout designs. • Good knowledge on Floor planning, critical 10 days ago
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Physical Design Manager Mulya Technologies - , , India power, performance (timing) and area targets. Expertise in meeting low power design goals would be a plus Experience on 3nm/4nm designs on TSMC/Samsung would be preferred Ability to anticipate / debug Yesterday
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VLSI - Physical Design Lead Engineer Eteros Technologies - , , India for digital and mixed signal SoCs • Preferably TSMC 7nm PNR sign-off experience using a full COT flow from RTL/gate to GDS • Experience in developing PNR methodology/flow to and supporting a larger PD team Yesterday
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