32 Verification System Verilog Jobs in Dadri
-
Senior Software Engineer Dadri, Uttar Pradesh, India methodologies. Fair understanding in one of the HDL (Verilog, System Verilog, VHDL or SystemC) Basics of Compiler Transformation and Optimizations B.Tech or M.Tech in CSE/EE/ECE from a reputed engineering college More than 30 days ago
-
Verification Lead Mirafra Technologies - Noida, Uttar Pradesh, India , System Verilog Methodology: UVM (preferred), OVM, VMM. Knowledge of scripting (Perl, C-shell) SVA will be a plus Good general verification experience with good academy results. Must-Have: SoC or IP 2 days ago
-
Staff/Sr Staff Design Verification Engineer [NOIDA] Renesas Electronics - Noida, Uttar Pradesh, India , Flash, LPDDR/DDR3/4) and memory controllers. Good knowledge of Verilog, System Verilog, C/C++, and Shell. Good knowledge in scripting like Perl, TCL, or Python is a plus Proficiency in Metric Driven 13 days ago
-
Infra DV Sr Engineer Qualcomm - Noida,Other Uttar Pradesh , Virtual Memory concepts, SoC system architecture Experience in developing Monitors, Scoreboards, Sequencers that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs 11 days ago
- Forum: Start a Discussion Join
-
SOC Engineering, Sr Engineer Synopsys - Noida the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. Responsible to implement and analyze system Verilog assertion and coverage (code Not disclosed INR 21 days ago
-
Senior Design Verification Engineer Synapse Design - Hybrid - Bengaluru, Hyderabad, Noida Role & responsibilities IP/Subsystem/SOC verification experience. Expertise in HVL and HDL (System Verilog, Verilog). Advanced knowledge of HVL methodology (UVM). Solid verification skills in problem Not disclosed INR 24 days ago
-
Cadence - Principle Software Engineer Noida, India Job Responsibilities & Skills: We need engines with good programing in C++/ C/SV. Experience with development and verification using System Verilog/HDL will be a plus. If you have any interest Not Mentioned 8 days ago
-
Member of Technical Staff Siemens - Noida knowledge of verification engineering and have between 2 - 8 years of working experience as well. Youve sound knowhow of System Verilog for test bench with exposure to verification methodologies like UVM, VMM Not disclosed INR 27 days ago
-
ASIC Digital Design, Staff Engineer Noida, India or MS/MTech with 6+ years of relevant experience in the verification of IP cores and/or SOC verification. - Must have experience in developing HVL (System Verilog or Vera or Specman) based test Not Mentioned 10 days ago
-
ASIC Digital Design, Staff Engineer Noida, India of functional verification flow with experience on industry standard development and verification tools and methodologies VMM, OVM/UVM and System Verilog Experience with System Verilog Assertions, code Not Mentioned 19 days ago
Top locations