38 Verification System Verilog Jobs in New Delhi
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Software Test Engineer GVR TECHNOLABS PRIVATE LIMITED - Delhi, IN / Verilog/ VHDL code review and reporting Third party library testing and report generation Verification of software tool qualification and documentation Impact analysis and change request-based testing More than 30 days ago
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LLM Hardware Design Developers Easy Recruit Global - India Gate, IN experience in hardware design development. Expertise in HDLs such as Verilog, System Verilog, VHDL, and SystemC. Expertise in scripting, front-end and verification workflows, and integrations within More than 30 days ago
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LLM Hardware Design Developers Easy Recruit Global - India Gate, Delhi, 110011 experience in hardware design development. Expertise in HDLs such as Verilog, System Verilog, VHDL, and SystemC. Expertise in scripting, front-end and verification workflows, and integrations within More than 30 days ago
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SoC Verification Engineer, Staff Synopsys Inc - Noida, Uttar Pradesh, India of the design. Responsible to implement and analyze system Verilog assertion and coverage (code, toggle, functional). Work alongside other members of the verification team to analyze, develop and execute More than 30 days ago
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Sr/ Staff/Sr Staff Verification IP Engineer Synopsys Inc - Noida, Uttar Pradesh, India , DIMMs, HBM2/3 protocol Hands on experience of developing complex protocols verification components with System Verilog, Verilog and OVM/UVM methodology; C/C++ knowhow is plus Good knowledge of simulation More than 30 days ago
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System-on-Chip Design (Synthesis) Engineer Optimhire IT Solutions Pvt Ltd - Noida,Other Uttar Pradesh , and area requirements. Key Responsibilities: Strong Domain Knowledge on RTL Design, implementation, and Timing analysis. Experience with RTL coding using Verilog/VHDL/System Verilog. Experience in micro 28 days ago
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ETHERNET Staff/Sr Staff Verification Engineer Synopsys Inc - Noida, Uttar Pradesh, India of developing complex protocols verification components with System Verilog, Verilog and OVM/UVM methodology; C/C++ knowhow is plus Good knowledge of simulation and/or emulation technologies with proven triage More than 30 days ago
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Senior Manager - ASIC Verification Synopsys Inc - Noida, Uttar Pradesh, India and Verification languages: SystemVerilog, Verilog • In-depth hands-on experiences in micro-architecture and RTL design, or verification methodologies such as UVM/OVM, functional formal, functional coverage More than 30 days ago
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Verification Engineer (3 – 7 years) Delhi, India Skills: UVM/OVM,Verilog,PCIe,Perl,Shell Scripting Job Locations: Delhi/NCR Total vacancies: 0 · Fluent in System Verilog HVL and hands-on on Verilog HDL. [Minimum 5 to 4 years of Experience] · Hands Not Mentioned More than 30 days ago
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Lead Verification Engineer Noida, India is a must. Design Verification experience verifying complex designs and leading projects from concept to verification closure. Strong hands-on UVM and System Verilog coding experience and functional Not Mentioned More than 30 days ago
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