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Logic Design/ASIC Design Engineer - RTL/Verilog/Timing Closure
Core Edge Solutions LLP - Bangalore/Trivandrum/Thiruvananthapuram, India
) in electrical engineering/ Microelectronics form a reputed institution, with a minimum 3 years of experience. - Candidate should have good knowledge of digital electronics and understanding of VLSI. - He / She
40
20 days ago
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