C++ Vc++ Jobs in New Delhi

Synopsys - Noida

BE / B Tech / ME/M Tech in electronics with 0-2 years experience in verification domain Required Some experience in Verilog / VHDL and or C languages is preferred Hands on experience in using Not disclosed INR

from: naukri.com - 18 days ago

Synopsys - Noida

of processor based Soc level verification which includes native ,Verilog ,system Verilog and UVM mix environment is desirable. Hand on experience with verification tools such as VCS, waveform analyzer and third Not disclosed INR

from: naukri.com (+1 source) - 18 days ago

Noida, India

of Analog Mixed signal IP along with functional requirements Experience and extensive hands on knowledge of HVLs (UVM/SV/C++/SC/e/VERA), HDLs (Verilog/VHDL),PLI/DPI, simulators (NCSim/VCS/ModelSim) Exposure Not Mentioned

from: Monsterindia.com - 5 days ago

Noida, India

-level goals and consistently meets schedules. Required B.E/B. Tech/M.E/M. Tech in electronics with 0-2 years experience in verification domain. Some experience in Verilog/VHDL and or C languages Not Mentioned

from: Monsterindia.com - 17 days ago

Noida, India

, Python, Perl and Bash . Expertise with industry-standard interfaces and protocols such as AMBA AXI or APB, I2C, and SPI. . Experience with Mobile Storage interfaces such as UFS, or eMMC . Familiarity Not Mentioned

from: Monsterindia.com - 7 days ago

Noida, India

scripting languages such Tcl, Python, Perl and Bash Expertise with industry-standard interfaces and protocols such as AMBA AXI or APB, I2C, and SPI. Experience with Mobile Storage interfaces such as UFS Not Mentioned

from: Monsterindia.com - 5 days ago

Noida, India

. Hand on experience with verification tools such as VCS, waveform analyzer and third party VIP integration (such as Synopsys VIPs) is must. Hands on experience in UVM. C/C++ ,System Verilog verification Not Mentioned

from: Monsterindia.com - 17 days ago

Noida, India

such as VCS, waveform analyzer and third party VIP integration (such as Synopsys VIPs) is must. Hands on experience in UVM. C/C++ ,System Verilog verification language. Good understanding of AXI-AMBA protocol Not Mentioned

from: Monsterindia.com - More than 30 days ago