Verilog Jobs in Pune
Performance Modeling Engineer
Cadence Design Systems - Pune, Maharashtra, India
Modeling (TLM) Basic understanding of performance principles, Queuing Theory, throughput/latency tradeoffs Additional Skills Understand RTL-Verilog, SV, UVM and experience analyzing waveforms Understand
from: linkedin.com - 8 days ago
Design Verification Engineer - SoC/UVM/System Verilog
Growel Softech Pvt. Ltd. - Pune, Maharashtra, IN
Design Verification Engineer Experience : 4 to 10 yrs Location : Bangalore Job Description : - Experience in leading a team along with Individual contribution. - Strong knowledge on Verilog, SV, UVM
from: adzuna.in - 22 days ago
Design Verification Engineer - SoC/UVM/System Verilog
Growel Softech Pvt. Ltd. - Pune, India
Design Verification EngineerExperience : 4 to 10 yrsLocation : BangaloreJob Description :- Experience in leading a team along with Individual contribution.- Strong knowledge on Verilog, SV, UVM- Work 20
from: hirist.com - 28 days ago
Senior FPGA Design Engineer
Pune, Maharashtra, India
for Ethernet switch features using Verilog or VHDL, ensuring high performance and low latency. Collaborate with cross-functional teams including hardware engineers, software engineers, and system architects
from: jobleads.co.in - 16 days ago
GVR TECHNOLABS PRIVATE LIMITED - Pune, IN
/ Verilog/ VHDL code review and reporting Third party library testing and report generation Verification of software tool qualification and documentation Impact analysis and change request-based testing
from: jobvertise.com - More than 30 days ago
Floating Point Datapath Microarchitect
Pune City, Maharashtra, India
-point execution. Knowledge of System Verilog, Verilog and/or VHDL. Experience with simulators and waveform debugging tools. Experience with datapath formal verification tools. Knowledge of logic design
from: jobleads.co.in - 12 days ago
Espressif Systems - Pune (Maharashtra)
Job Description 503 Basic Qualications: 1. M.Tech/B. Tech in the field of VLSI/Electronics engineering. 2. Proficiency in System Verilog for RTL logic design and verification. 3. Experience
from: timesjobs.com - 28 days ago
ASIC Digital Design, Staff Engineer
Pune, India
Job Description and Requirements : Key responsibilities: Identify verification environment requirements from its various sources (Specifications, Design functionality, Interfaces, etc …) Generate Not Mentioned
from: Monsterindia.com - 18 days ago
ASIC Digital Design, Staff Engineer
Pune, India
Job Description and Requirements Job Description and Requirements : Key responsibilities: Identify verification environment requirements from its various sources (Specifications, Design functionality Not Mentioned
from: Monsterindia.com - 17 days ago
ASIC Digital Design, Engineer
Pune, India
. Hands on experience with Synthesizable Verilog/ System Verilog RTL coding for ASIC designs and Simulation tools Lint, CDC, Synthesis flow and static timing flows, Formal checking, etc is a must Not Mentioned
from: Monsterindia.com - More than 30 days ago
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