Vhdl Jobs in Pune
Senior Embedded Software Engineer
QUASAR SOFTWARE DEFINED RADIO - Pune, Maharashtra, India
incorporating Xilinx Vivado & Xilinx SDK. Experience with Xilinx Zynq platform, Vivado Tools (10G Ethernet IP). Understanding of FPGA HDL (VHDL, Verilog, System Verilog) and/or FPGA PL/RTL. Experienced in RTOS
from: linkedin.com (+1 source) - 12 days ago
Mixed Signal ASIC Design
VASBEAM Pvt Ltd - Pune, Maharashtra, India
and behavioural modeling using MATLAB, System Verilog, Verilog-A/AMS. Experience with HDL languages Verilog and/or VHDL is desired. Scripting skills: Python, Perl and C is a plus. · Experience with design
from: linkedin.com - More than 30 days ago
FPGA Engineer - RTL/VHDL
M Systems - Hyderabad/Pune, India
Job requirements : Experience : 5-10 YearsEducation: B.Tech/BE/ME/M.TechTechnical Skills :- Good in RTL coding, VHDL, Test Bench, Validation, and Simulators.- High & low-level design- Experience 40
from: hirist.com - 23 days ago
ASIC Digital Design, Principal Engineer
Pune, Maharashtra, India
, verification and implement phases of state-of-the-art products. Key responsibilities: Identify verification environment requirements from its various sources (Specifications, Design functionality, Interfaces
from: jobleads.co.in - More than 30 days ago
Senior FPGA Design Engineer
Pune, Maharashtra, India
, including VLAN tagging, frame forwarding, MAC address learning, and multicast filtering. Implement RTL code for Ethernet switch features using Verilog or VHDL, ensuring high performance and low latency
from: jobleads.co.in - More than 30 days ago
Mixed Signal ASIC Design Lead - System Verilog
ACZ Global Private Limited - Pune, India
Verilog and/or VHDL is desired.- Scripting skills like Python, Perl and C is a plus.- Experience with design, implementation, and development environments for reconfigurable systems (such as FPGAs 40
from: hirist.com - More than 30 days ago
Intelliswift - Pune
DescriptionMust-Have it: • Hands-on experience in VHDL and/or Verilog programming and setting up test benches for verification of FPGA /CPLD logic. • Requirements, design, implementation, test Not disclosed INR
from: naukri.com - 13 days ago
ASIC Digital Design, Staff Engineer
Pune, India
and implement phases of state-of-the-art products. Key responsibilities: Identify verification environment requirements from its various sources (Specifications, Design functionality, Interfaces, etc …) Generate Not Mentioned
from: Monsterindia.com - 16 days ago
ASIC Digital Design, Principal Engineer
Pune, India
, verification and implement phases of state-of-the-art products. Key responsibilities: Identify verification environment requirements from its various sources (Specifications, Design functionality, Interfaces Not Mentioned
from: Monsterindia.com - More than 30 days ago
ASIC Digital Verification Engineer, Sr II
Pune, India
will be involved at specify, verification and implement phases of state-of-the-art products. Key Responsibilities Identify verification environment requirements from its various sources (Specifications, Design Not Mentioned
from: Monsterindia.com - 4 days ago
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