9 Verification System Verilog Jobs in Pune
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Design Verification Engineer - SoC/UVM/System Verilog Growel Softech Pvt. Ltd. - Pune, Maharashtra, IN Design Verification Engineer Experience : 4 to 10 yrs Location : Bangalore Job Description : - Experience in leading a team along with Individual contribution. - Strong knowledge on Verilog, SV, UVM -... More than 30 days ago
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Senior FPGA Design Engineer Pune, Maharashtra, India for Ethernet switch features using Verilog or VHDL, ensuring high performance and low latency. Collaborate with cross-functional teams including hardware engineers, software engineers, and system architects More than 30 days ago
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Embedded C/C++ GVR TECHNOLABS PRIVATE LIMITED - Pune, IN / Verilog/ VHDL code review and reporting Third party library testing and report generation Verification of software tool qualification and documentation Impact analysis and change request-based testing More than 30 days ago
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Floating Point Datapath Microarchitect Pune City, Maharashtra, India -point execution. Knowledge of System Verilog, Verilog and/or VHDL. Experience with simulators and waveform debugging tools. Experience with datapath formal verification tools. Knowledge of logic design More than 30 days ago
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Digital Design Verification Staff Engineer Pune, India , other networking protocols Test planning, Coverage and Assertion planning. Hands on experience with System Verilog, mythologies like VMM/UVM, simulation and debug tools. Experience with Version Control Not Mentioned More than 30 days ago
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Senior Staff Engineer I - RTL Design Bengaluru / Bangalore, Pune, India or FPGA development. Protocol knowledge (UCIe, PCIe, CXL, HBM, AMBA SoC bus Protocols). Solid experience with Verilog and System Verilog. Experience with Lint, CDC, Synthesis, Power analysis, and LEC tools Not Mentioned More than 30 days ago
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Lead I - Embedded Software Pune, India Linux and Android) Comprehension of ASPICE & ISO26262 process Knowledge in Pre-Silicon Verification environments for simulation and Emulation/FPGA platform Experience with System Verilog IP/Subsystem Not Mentioned More than 30 days ago
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Staff Engineer I - VLSI Bengaluru / Bangalore, Pune, India functional verification. Experience with digital verification aspects such as constrained random verification, functional coverage, code coverage, assertions, methodology & philosophy. Expert in System Verilog Not Mentioned More than 30 days ago
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Floating Point Datapath Designer Pune, India Knowledge of System Verilog, Verilog and/or VHDL Experience with simulators and waveform debugging tools. Experience with datapath formal verification tools Knowledge of logic design principles along Not Mentioned More than 30 days ago
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